1. Field of the Invention
The present invention relates generally to low-noise amplifiers and more specifically to low-noise amplifiers having a high gain at high frequencies using magnetic feedback loops.
2. Prior Art
Technology advances in CMOS processes lead to nanometer (nm) scale transistor structures, suitable for high frequency operation. This facilitates the implementation of Systems on Chip (SoC) with numerous advantages regarding size, cost, and package. In addition, design in nm-scale allows for the supply voltage of the digital circuitry to be reduced to or below 1 V. On the other hand, shrinking of the supply voltage imposes many challenges in the design of the analog part of the system. In integrated low-noise amplifier (LNA) design, classical topologies, including the vastly used cascode topology, are impractical when the lowest possible supply voltage is desired. It is thus imperative for new design topologies to be introduced.
Single transistor LNAs that successfully use magnetic negative feedback for MOS gate-drain capacitance (Cgd) neutralization are known in the art. This ensures high reverse isolation at the cost of reduced gain. However, the low output impedance of the amplifier is not optimal for driving large capacitive on-chip loads. Transformers can be used to provide magnetic feedback that can be modeled as shown in FIG. 1. The nature of the feedback depends on the direction of the currents I1 and I2. In FIG. 1, the transformer provides positive feedback at the input. In this notation, M is the mutual inductance and equals to M=k√{square root over (L1L2)}, where k is the coupling coefficient. A single transformer LNA is depicted in FIG. 2, whereas in FIG. 3 the corresponding small signal model is presented. The topology is designed to provide negative feedback, represented by the coupling coefficient k12, in order to neutralize the capacitance Cgd of the transistor and thus increase the reverse isolation of the topology. The transistor M1 is the amplifying transistor, while inductors L1 and L2 are the degeneration and load inductors, respectively. The capacitance C1 represents the equivalent load of the mixer input stage that typically follows the LNA.
It would therefore be advantageous to provide a LNA that overcomes the deficiencies of prior art solutions. Specifically, such a LNA should provide high gain at high frequencies, achieve a large reverse isolation, enable operation at low voltage levels, and be capable of driving large capacitive on-chip loads. It would be further advantageous if the proposed solution overcomes the strict requirements on mutual inductance coefficients and individual inductors present in prior art solutions.